This invention relates to an amplifier arrangement comprising a first transistor having a control electrode coupled to an input terminal for receiving an input signal, having a first main electrode coupled to a first supply-voltage terminal, and having a second main electrode, a second transistor having a control electrode, having a first main electrode coupled to the second main electrode of the first transistor, and having a second main electrode coupled to an output terminal for supplying an output signal, and a control amplifier having an inverting input coupled to the second main electrode of the first transistor, and having an output coupled to the control electrode of the second transistor.
Such an amplifier arrangement can be used in general for amplifying a signal in integrated semiconductor circuits.
Such an amplifier arrangement is known inter alia from European Patent Application EP-A 0,397,240, which corresponds to U.S. Pat. No. 5,039,954 Aug. 13, 1991. The known amplifier arrangement amplifies an input signal applied to the input terminal so as to obtain an output signal on the output terminal, the control amplifier maintaining a substantially constant potential on the second main electrode of the first transistor. As a result of the substantially constant potential the known amplifier arrangement can provide a high gain, although in some cases the output impedance and hence the internal gain of the amplifier arrangement are too low, which is a disadvantage.